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connection diagram 8-lead dip and soic v s disable 1 2 3 4 8 7 6 5 nc = no connect nc nc output Cinput input Cv s ad8041 (top view) rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 160 mhz rail-to-rail amplifier with disable ad8041 * features fully specified for +3 v, +5 v, and 5 v supplies output swings rail to rail input voltage range extends 200 mv below ground no phase reversal with inputs 1 v beyond supplies disable/power-down capability low power of 5.2 ma (26 mw on 5 v) high speed and fast settling on 5 v: 160 mhz C3 db bandwidth (g = +1) 160 v/ s slew rate 30 ns settling time to 0.1% good video specifications (r l = 150 , g = +2) gain flatness of 0.1 db to 30 mhz 0.03% differential gain error 0.03 differential phase error low distortion C69 dbc worst harmonic @ 10 mhz outstanding load drive capability drives 50 ma 0.5 v from supply rails cap load drive of 45 pf applications power sensitive high speed systems video switchers distribution amplifiers a/d driver professional cameras ccd imaging systems ultrasound equipment (multichannel) single-supply multiplexer product description the ad8041 is a low power voltage feedb ack, high-speed ampli- fier designed to operate on +3 v, +5 v, or 5 v supplies. it has true single supply capability with an input voltage range extending 200 mv below the negative rail and within 1 v of the positive rail. 5v 2.5v 0v 200ns 1v figure 1. output swing: g = C1, v s = 5 v the output voltage swing extends to within 50 mv of each rail, providing the maximum output dynamic range. additionally, it features gain flatness of 0.1 db to 30 mhz while offering differ- ential gain and phase error of 0.03% and 0.03 on a single 5 v supply. this makes the ad8041 ideal for professional video electronics such as cameras, video switchers or any high-speed portable equipment. the ad8041? low distortion and fast settling make it ideal for buffering high-speed a-to-d converters. the ad8041 has a high-speed disable feature useful for mul- tiplexing or for reducing power consumption (1.5 ma). the disable logic interface is compatible with cmos or open- collector logic. the ad8041 offers low power supply current of 5.8 ma max and can run on a single 3 v power supply. these features are ideally suited for portable and battery powered applications where size and power are critical. the wide bandwidth of 160 mhz along with 160 v/ s of slew rate on a single 5 v supply make the ad8041 useful in many general purpose high-speed applications where dual power supplies of up to 6 v and single supplies from 3 v to 12 v are needed. the ad8041 is available in 8-lead plastic dip and soic over the industrial temperature range of ?0 c to +85 c. frequency C mhz v s = 5v g = +2 r f = 400 0 100 normalized gain C db 80 60 40 20 0 2 1 C 2 C 1 C 8 C 7 C 6 C 5 C 4 C 3 figure 2. frequency response: g = +2, v s = 5 v one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 * protected under u.s. patent no. 5,537,079.
ad8041?pecifications rev. a C2C (@ t a = 25 c, v s = 5 v, r l = 2 k to 2.5 v, unless otherwise noted.) ad8041a parameter conditions min typ max unit dynamic performance 3 db small signal bandwidth, v o < 0.5 v p-p g = +1 130 160 mhz bandwidth for 0.1 db flatness g = +2, r l = 150 ? 30 mhz slew rate g = ?, v o = 2 v step 130 160 v/ s full power response v o = 2 v p-p 24 mhz settling time to 0.1% g = ?, v o = 2 v step 35 ns settling time to 0.01% 55 ns noise/distortion performance total harmonic distortion f c = 5 mhz, v o = 2 v p-p, g = +2, r l = 1 k ? ?2 db input voltage noise f = 10 khz 16 nv/ hz input current noise f = 10 khz 600 fa/ hz differential gain error (ntsc) g = +2, r l = 150 ? to 2.5 v 0.03 % g = +2, r l = 75 ? to 2.5 v 0.01 % differential phase error (ntsc) g = +2, r l = 150 ? to 2.5 v 0.03 degrees g = +2, r l = 75 ? to 2.5 v 0.19 degrees dc performance input offset voltage 27mv t min to t max 8mv offset drift 10 v/ c input bias current 1.2 3.2 a t min to t max 3.5 a input offset current 0.2 0.5 a open-loop gain r l = 1 k ? 86 95 db t min to t max 90 db input characteristics input resistance 160 k ? input capacitance 1.8 pf input common-mode voltage range ?.2 to +4 v common-mode rejection ratio v cm = 0 v to 3.5 v 74 80 db output characteristics output voltage swing: r l = 10 k ? 0.05 to 4.95 v output voltage swing: r l = 1 k ? 0.35 to 4.75 0.1 to 4.9 v output voltage swing: r l = 50 ? 0.4 to 4.4 0.3 to 4.5 v output current v out = 0.5 v to 4.5 v 50 ma short circuit current sourcing 90 ma sinking 150 ma capacitive load drive g = +1 45 pf power supply operating range 312v quiescent current 5.2 5.8 ma quiescent current (disabled) 1.4 1.7 ma power supply rejection ratio v s = 0, +5 v, 1 v 72 80 db disable characteristics v o = 2 v p-p @ 10 mhz, g = +2 turn-off time r f = r l = 2 k ? 120 ns turn-on time r f = r l = 2 k ? 230 ns off isolation (pin 8 tied to ? s )r l = 100 ? , f = 5 mhz, g = +2, r f = 1 k ? 70 db off voltage (device disabled) rev. a C3C ad8041 specifications (@ t a = 25 c, v s = 3 v, r l = 2 k to 1.5 v, unless otherwise noted) ad8041a parameter conditions min typ max unit dynamic performance 3 db small signal bandwidth, v o < 0.5 v p-p g = +1 120 150 mhz bandwidth for 0.1 db flatness g = +2, r l = 150 ? 25 mhz slew rate g = ?, v o = 2 v step 120 150 v/ s full power response v o = 2 v p-p 20 mhz settling time to 0.1% g = ?, v o = 2 v step 40 ns settling time to 0.01% 55 ns noise/distortion performance total harmonic distortion f c = 5 mhz, v o = 2 v p-p, g = ?, r l = 100 ? ?5 db input voltage noise f = 10 khz 16 nv/ hz input current noise f = 10 khz 600 fa/ hz differential gain error (ntsc) g = +2, r l = 150 ? to 1.5 v, input v cm = 1 v 0.07 % differential phase error (ntsc) g = +2, r l = 150 ? to 1.5 v, input v cm = 1 v 0.05 degrees dc performance input offset voltage 27mv t min to t max 8mv offset drift 10 v/ c input bias current 1.2 3.2 a t min to t max 3.5 a input offset current 0.2 0.6 a open-loop gain r l = 1 k ? 85 94 db t min to t max 89 db input characteristics input resistance 160 k ? input capacitance 1.8 pf input common-mode voltage range ?.2 to +2 v common-mode rejection ratio v cm = 0 v to 1.5 v 72 80 db output characteristics output voltage swing: r l = 10 k ? 0.05 to 2.95 v output voltage swing: r l = 1 k ? 0.45 to 2.7 0.1 to 2.9 v output voltage swing: r l = 50 ? 0.5 to 2.6 0.25 to 2.75 v output current v out = 0.5 v to 2.5 v 50 ma short circuit current sourcing 70 ma sinking 120 ma capacitive load drive g = +1 40 pf power supply operating range 312v quiescent current 5.0 5.6 ma quiescent current (disabled) 1.3 1.5 ma power supply rejection ratio v s = 0, +3 v, 0.5 v 68 80 db disable characteristics v o = 2 v p-p @ 10 mhz, g = +2 turn-off time r f = r l = 2 k ? 90 ns turn-on time r f = r l = 2 k ? 170 ns off isolation (pin 8 tied to ? s )r l = 100 ? , f = 5 mhz, g = +2, r f = 1 k ? 70 db off voltage (device disabled) ad8041a parameter conditions min typ max unit dynamic performance 3 db small signal bandwidth, v o < 0.5 v p-p g = +1 140 170 mhz bandwidth for 0.1 db flatness g = +2, r l = 150 ? 32 mhz slew rate g = ?, v o = 2 v step 140 170 v/ s full power response v o = 2 v p-p 26 mhz settling time to 0.1% g = ?, v o = 2 v step 30 ns settling time to 0.01% 50 ns noise/distortion performance total harmonic distortion f c = 5 mhz, v o = 2 v p-p, g = +2, r l = 1 k ? ?7 db input voltage noise f = 10 khz 16 nv/ hz input current noise f = 10 khz 600 fa/ hz differential gain error (ntsc) g = +2, r l = 150 ? 0.02 % g = +2, r l = 75 ? 0.02 % differential phase error (ntsc) g = +2, r l = 150 ? 0.03 degrees g = +2, r l = 75 ? 0.10 degrees dc performance input offset voltage 27mv t min to t max 8mv offset drift 10 v/ c input bias current 1.2 3.2 a t min to t max 3.5 a input offset current 0.2 0.6 a open-loop gain r l = 1 k ? 90 99 db t min to t max 95 db input characteristics input resistance 160 k ? input capacitance 1.8 pf input common-mode voltage range ?.2 to +4 v common-mode rejection ratio v cm = ? v to +3.5 v 72 80 db output characteristics output voltage swing: r l = 10 k ? ?.95 to +4.95 v output voltage swing: r l = 1 k ? ?.45 to +4.6 ?.8 to +4.8 v output voltage swing: r l = 50 ? ?.3 to +3.2 ?.5 to +3.8 v output current v out = ?.5 v to +4.5 v 50 ma short circuit current sourcing 100 ma sinking 160 ma capacitive load drive g = +1 50 pf power supply operating range 312v quiescent current 5.8 6.5 ma quiescent current (disabled) 1.6 2.2 ma power supply rejection ratio v s = ? v, +5 v, 1 v 68 80 db disable characteristics v o = 2 v p-p @ 10 mhz, g = +2 turn-off time r f = 2 k ? 120 ns turn-on time r f = 2 k ? 320 ns off isolation (pin 8 tied to ? s )r l = 100 ? , f = 5 mhz, g = +2, r f = 1 k ? 70 db off voltage (device disabled) ad8041 rev. a C5C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 v internal power dissipation 2 plastic dip package (n) . . . . . . . . . . . . . . . . . . . 1.3 watts small outline package (r) . . . . . . . . . . . . . . . . . . 0.9 watts input voltage (common mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 3.4 v output short circuit duration . . . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range n, r . . . . . . . . ?5 c to +125 c operating temperature range (a grade) . . . ?0 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for the device in free air: 8-lead plastic dip package: ja = 90 c/w. 8-lead soic package: ja = 155 c/w. maximum power dissipation the maximum power that can be safely dissipated by the ad8041 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150 c. exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175 c for an extended period can result in device failure. while the ad8041 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction tem- perature (150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves. maximum power dissipation C watts ambient temperature C c 2.0 1.5 0 C 50 90 C 40 C 30 C 20 C 10 0 102030 50607080 40 1.0 0.5 8-lead plastic dip package 8-lead soic package t j = 150 c figure 3. maximum power dissipation vs. temperature caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8041 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide temperature package package model range description options ad8041an ?0 c to +85 c 8-lead plastic dip n-8 ad8041ar ?0 c to +85 c 8-lead plastic soic so-8 ad8041ar-reel ?0 c to +85 c 13" tape and reel so-8 AD8041AR-REEL7 ?0 c to +85 c 7" tape and reel so-8 ad8041-eb evaluation board 5962-9683901mpa * ?5 c to +125 c 8-lead cerdip q-8 * refer to official dscc drawing for tested specifications. warning! esd sensitive device
v os C mv 30 15 0 25 20 10 5 C 66 C 5 C 4 C 3 C 2 C 1012345 number of parts in bin v s = 2.5v t a = 25 c 91 parts mean = +0.21 std deviation = 1.47 tpc 1. typical distribution of v os v os drift C v/ c 0.20 0.15 0 C 10 10 C 7.5 probability density C 5 C 2.5 0 2.5 5 7.5 0.10 0.05 mean = 0.02 v/ c std dev = 2.87 v/ c sample size = 45 tpc 2. v os drift over C40 c to +85 c temperature C c 2 1.5 0 C 45 85 C 35 C 25 C 15 C 5 5 15 25 35 45 55 65 75 1 0.5 input bias current C a v s = 5v v cm = 0v tpc 3. i b vs. temperature C6C rev. a ad8041 typical performance characteristics load resistance C 100 70 95 90 85 80 75 0 2000 250 500 750 1000 1250 1500 1750 v s = 5v t a = 25 c open-loop gain C db tpc 4. open-loop gain vs. r l to 25 c temperature C c 100 97 85 C 60 C 40 C 20 0 20 40 60 80 100 120 94 91 88 open-loop gain C db v s = 5v r l = 1k to 2.5v tpc 5. open-loop gain vs. temperature output voltage C volts 100 70 40 90 80 60 50 05 0.5 1 1.5 2 2.5 3 3.5 4 4.5 r l = 500 to 2.5v v s = 5v r l = 50 to 2.5v open-loop gain C db tpc 6. open-loop gain vs. output voltage
ad8041 rev. a C7C frequency C hz 200 150 0 100 50 10 100k 100 input voltaage noise C nv/ hz 1k 10k tpc 7. input voltage noise vs. frequency fundamental frequency C mhz C 30 C 40 C 100 110 2 total harmonic distortion C dbc C 60 C 70 C 80 C 90 C 50 3456789 v s = 3v, a v = C 1, r l = 100 to 1.5v v s = 5v, a v = 1, r l = 1k to 2.5v v s = 5v, a v = 2, r l = 100 to 2.5v v s = 5v, a v = 2, r l = 1k to 2.5v v s = 5v, a v = 1, r l = 100 to 2.5v tpc 8. total harmonic distortion output voltage C v pp 0 1.5 0.5 1 2 2.5 3 3.5 4 4.5 5 worst harmonic C dbc C 140 C 30 C 40 C 50 C 70 C 100 C 80 C 90 C 60 C 110 C 120 C 130 10mhz 5mhz 1mhz v s = 5v r l = 2k to 2.5v g = +2 tpc 9. worst harmonic vs. output voltage diff phase C degrees diff gain C % 11th 1st 6th 2nd 3rd 4th 5th 7th 8th 9th 10th C 0.005 0.015 0.005 0.025 0.020 0.010 0.000 0.030 C 0.010 0.035 v s = 5v g = +2 r l = 150 to 2.5v 11th 1st 6th 2nd 3rd 4th 5th 7th 8th 9th 10th v s = 5v g = +2 r l = 150 C 0.005 0.015 0.005 0.025 0.020 0.010 0.000 0.030 C 0.010 0.035 v s = 5v g = +2 r l = 150 to 2.5v v s = 5v g = +2 r l = 150 dc output level C 100 ire max tpc 10. differential gain and phase errors frequency C mhz 6.5 6.4 5.5 6.3 6.2 6.1 6.0 5.9 5.8 5.7 5.6 1 500 10 100 32.4mhz v s = 5v g = +2 r l = 150 to 2.5v r f = 402 closed-loop gain C db tpc 11. 0.1 db gain flatness C 10 40 30 60 0 50 10 20 80 90 70 open-loop gain C db C 180 0 C 90 90 180 270 phase C c 360 450 C 270 C 360 C 450 500 0.1 0.01 100 10 frequency C mhz v s = 5v r l = 2k to 2.5v c l = 5pf to 2.5v phase gain tpc 12. open-loop gain and phase vs. frequency
frequency C mhz 5 4 C 5 3 2 1 0 C 1 C 2 C 3 C 4 1 500 10 100 v s = 5v r l = 2k to 2.5v c l = 5pf g = +1 t = +125 c t = +25 c t = C 55 c closed-loop gain C db tpc 13. closed-loop frequency response vs. temperature frequency C mhz 5 4 C 5 3 2 1 0 C 1 C 2 C 3 C 4 1 500 10 100 g = +1 r l = 2k c l = 5pf v s = 3v r l & c l to 1.5v v s = 5v closed-loop gain C db v s = 5v r l & c l to 2.5v tpc 14. closed-loop frequency response vs. supply frequency C mhz 100 10 1 0.1 0.01 1 500 10 100 0.1 0.01 g = +1 v s = 5v output resistance C tpc 15. output resistance vs. frequency rev. a C8C input step C volts p-p time C ns 50 40 10 0.5 2 1 1.5 30 20 v s = 3v, 0.1% v s = 5v, 0.1% v s = 3v, 1% v s = 5v, 1% g = C 1 tpc 16. settling time vs. input step frequency C mhz C 10 C 40 C 60 C 80 C 100 C 20 C 30 C 50 C 70 C 90 C 110 1 500 10 100 0.1 0.01 cmrr C db v s = +3v and 5v tpc 17. cmrr vs. frequency load current C ma output saturation voltage C mv 1000 10 0 0.001 0.01 100 0.1 1 10 100 v ol , C 55 c + 5 v C v oh , + 12 5 c v ol , +125 c v s = 5v +5v C v o h , C 55 c tpc 18. output saturation voltage vs. load current ad8041 typical performance characteristics
ad8041 rev. a C9C temperature C c 8 5 2 C 60 C 40 C 20 0 20 40 60 80 100 120 supply current C ma 7 6 4 3 v s = 5v v s = 5v v s = 3v tpc 19. supply current vs. temperature frequency C mhz 40 C 20 C 60 C 100 C 140 20 0 C 40 C 80 C 120 C 160 1 500 10 100 0.1 0.01 psrr C db v s = 5v C psrr +psrr tpc 20. psrr vs. frequency 10 9 0 6 3 2 1 8 7 4 5 v out p-p C volts frequency C mhz v s = 5v r l = 2k 0.1 1000 1 10 100 tpc 21. output voltage swing vs. frequency series resistance C 90 10 80 50 40 30 20 70 60 0 060 10 20 30 40 50 v in 100k r series c load 1k 20 phase margin 45 phase margin v s = 5v capacitive load C pf tpc 22. capacitive load vs. series resistance frequency C mhz 5 4 C 5 normalized output C db 3 2 1 0 C 1 C 2 C 3 C 4 1 500 10 100 g = 2 g = 10 g = 5 g = 2, r f = 402 v s = 5v r l = 5k to 2.5v r f = 2k 324*. !
+ 4 9: & 1.600v 1.550v 1.500v 1.450v 1.400v 1.425v 1.475v 1.525v 1.575v 10ns 50mv v i n = 0.1v p-p r l = 2k v s = 3v g = +1 tpc 24. pulse response, v s = 3 v
ad8041 typical performance characteristics C10C rev. a 5v 4v 3v 2v 1v 0v 200 s 1v 0.111v min r l = 150 to 2.5v 4.840v max tpc 25a. 5v 4v 3v 2v 1v 0v 200 s 1v r l = 150 to gnd 4.741v max 0.043v min tpc 25b. tpc 25a-b. output swing vs. load reference voltage, v s = 5 v, g = C1 4.5v 3.5v 2.5v 1.5v 0.5v 40ns 1v v s = 5v g = +2 r l = 2k v in = 1v p-p tpc 26. one volt step response, v s = 5 v, g = +2 2.6v 2.55v 2.5v 2.45v 2.4v v s = 5v g = +1 r l = 2k v l = 5pf 40ns 50mv tpc 27. 100 mv step response, v s = 5 v, g = +1 3v 2.5v 2v 1.5v 1v 0.5v 0v 2 s 500mv v in = 3v p-p f = 0.1mhz r l = 2k v s = 3v g = C 1 tpc 28. output swing, v s = 3 v, v in = 3 v p-p 3v 2.5v 2v 1.5v 1v 0.5v 0v 2 s 500mv v in = 2.8v p-p f = 0.8mhz r l = 2k v s = 3v g = C 1 tpc 29. output swing, v s = 3 v, v in = 2.8 v p-p
ad8041 rev. a C11C overdrive recovery overdrive of an amplifier occurs when the output and/or input range are exceeded. the amplifier must recover from this over- drive condition. as shown in figure 4, the ad8041 recovers within 50 ns from negative overdrive and within 25 ns from positive overdrive. 5v 2.5v 0v 40ns 50mv output input g = +2 v s = 5v figure 4. overdrive recovery circuit description the ad8041 is fabricated on analog devices?proprietary extra-fast complementary bipolar (xfcb) process which enables the construction of pnp and npn transistors with similar f t s in the 2 ghz? ghz region. the process is dielectrically isolated to eliminate the parasitic and latch-up problems caused by junction isolation. these features allow the construction of high frequency, low distortion amplifiers with low supply currents. this design uses a differential output input stage to maximize bandwidth and headroom (see figure 5). the smaller signal swings required on the first stage outputs (nodes s1p, s1n) reduce the effect of nonlinear currents due to junction capacitances and improve the distortion performance. with this design harmonic distortion of better than ?5 db @ 1 mhz into 100 ? with v out = 2 v p-p (g ain = +2) on a single 5 volt supply is achieved. the complementary common-emitter design of the output stage provides excellent load drive without the need for emitter followers, thereby improving the output range of the device considerably with respect to conventional op amps. high output drive capa- bility is provided by injecting all output stage predriver currents directly into the bases of the output devices q8 and q36. bias- ing of q8 and q36 is accomplished by i8 and i5, along with a common-mode feedback loop (not shown). this circuit topology allows the ad8041 to drive 50 ma of output current with the outputs within 0.5 v of the supply rails. on the input side, the device can handle voltages from ?.2 v below the negative rail to within 1.2 v of the positive rail. exceed- ing these values will not cause phase reversal; however, the input esd devices will begin to conduct if the input voltages exceed the rails by greater than 0.5 v. a ?ested integrator?topology is used in the ad8041 (see small-signal schematic shown in figure 6). the output stage can be modeled as an ideal op amp with a single-pole response and a unity-gain frequency set by transconductance g m2 and capacitor c9. r1 is the output resistance of the input stage; g m is the input transconductance. c7 and c9 provide miller com- pensation for the overall op amp. the unity gain frequency will occur at g m /c9. solving the node equations for this circuit yields: v vi a sr c a s g c out m = ++ ? ? ? ? ? ? + ? ? ? ? ? ? 0 19 21 1 3 1 2 ([( )]) where a 0 = g m g m2 r2 r1 (open-loop gain of op amp) a 2 = g m2 r2 (open-loop gain of output stage) the first pole in the denominator is the dominant pole of the amplifier, and occurs at about 180 hz. this equals the input stage output impedance r1 multiplied by the miller-multiplied value of c9. the second pole occurs at the unity-gain bandwidth of the output stage, which is 250 mhz. this type of architecture allows more open-loop gain and output drive to be obtained than a standard two-stage architecture would allow. output impedance the low frequency open-loop output impedance of the common emitter output stage used in this design is approximately 6.5 k ? . while this is significantly higher than a typical emitter follower output stage, when connected with feedback the output imped- ance is reduced by the open-loop gain of the op amp. with 110 db of open-loop gain the output impedance is reduced to less than 0.1 ? . at higher frequencies the output impedance will rise as the open-loop gain of the op amp drops; however, the out- put also becomes capacitive due to the integrator capacitors c9 and c3. this prevents the output impedance from ever becoming excessively high (see tpc 15), which can cause stability prob- lems when driving capacitive loads. in fact, the ad8041 has excellent cap-load drive capability for a high-frequency op amp. tpc 22 demonstrates that the ad8041exhibits a 45 margin while driving a 20 pf direct capacitive load. in addition, run- ning the part at higher gains will also improve the capacitive load drive capability of the op amp. sin r21 r3 v ee q11 q3 i10 r26 r39 q5 q4 q40 i7 r2 r15 q13 q17 r5 c7 q2 sip q22 q7 q21 q24 r23 r27 i2 i3 i1 q51 q25 q50 q39 q47 q27 q31 q23 i9 i5 v ee v cc i8 q36 q8 v out c3 c9 v cc v in p v in n v ee figure 5. ad8041 simplified schematic
rev. a C12C ad8041 r2 c3 g m2 v out r1 c9 g m vi s1n s1p c7 r1 g m vi figure 6. small signal schematic disable operation the ad8041 has an active-low disable pin, which can be used to three-state the output of the part and also lower its supply current. if the disable pin is left floating, the part is enabled and will perform normally. if the disable pin is pulled to 2.5 v (min) below the positive supply, output of the ad8041 will be disabled and the nominal supply current will drop to less than 1.6 ma. for best isolation, the disable pin should be pulled to as low a voltage as possible; ideally, the negative supply rail. the disable pin on the ad8041 allows it to be configured as an 2:1 mux as shown in figure 7 and can be used to switch many types of high speed signals. higher order multiplexers can also be built. the break-before-make switching time is approximately 50 ns to disable the output and 300 ns to enable the output. 6 4 7 3 2 ad8041 330 50 10 f 5v 330 8 6 4 7 3 2 ad8041 330 50 10 f 5v 330 8 13 12 11 10 74hc04 50 g = +2 g = +2 ch0 5mhz ch1 10mhz figure 7. 2:1 multiplexer 10 0% 100 90 200ns 1v v s = 5v figure 8. 2:1 multiplexer performance single supply a/d conversion figure 9 shows the ad8041 driving the analog inputs of the ad9050 in a dc coupled system with single-ended signals. all components are powered from a single 5 v supply. the ad820 is used to offset the ground referenced input signal to the level required by the ad9050. the ad8041 is used to add in the o ffset with the ground referenced input signal and buffer the in put to ad9050. the nominal input range of the ad9050 is 2.8 v 0.1 f 5v ad8041 2.8v C 3.8v 3.3v 5v ad9050 10 9 1k v in C 0.5v to +0.5v 1k 1k 0.1 f 5v ad820 1k figure 9. 10-bit, 40 msps a/d conversion and 3.8 v (1 v p-p centered at 3.3 v). this circuit p rovides 40 msps analog-to-digital conversion on just 330 mw of power while delivering 10-bit performance. 0 C 10 C 100 C 60 C 70 C 80 C 90 C 40 C 50 C 30 C 20 f 1 = 4.9mhz fundamental = 0.6db 2nd harmonic = 66.9db 3rd harmonic = 74.7db snr = 55.2db noise floor = C 86.1db encode frequency = 40mhz figure 10. fft output of circuit in figure 9
ad8041 rev. a C13C applications rgb buffer the ad8041 can provide buffering of rgb signals that include ground while operating from a single 3 v or 5 v supply. the signals that drive an rgb monitor are usually supplied by current output dacs that operate from a 5 v only supply. these can triple dacs like the adv7120 and adv7122 from analog devices or integrate into the graphics controller ic as in most pcs these days. during the horizontal blanking interval the currents output from the dacs go to zero and the rgb signals are pulled to ground via the termination resistors. if more than one rgb monitor is desired, it cannot simply be connected in parallel because it will provide an additional termination. therefore, buffering must be provided before connecting a second monitor. since the rgb signals include ground as part of their dynamic output range, it has previously been required to use a dual sup- ply op amp to provide this buffering. in some systems this is the only component that requires a negative supply so it can be quite inconvenient to incorporate this multiple monitor feature. figure 11 shows a schematic of one channel of a single supply gain-of-two buffer for driving a second rgb monitor. no cur- rent is required when the amplifier output is at ground. the termination resistor at the monitor helps pull the output down at low voltage levels. 6 4 7 3 2 ad8041 1k 75 10 f 8 75 r, g or b nc 0.1 f 1k primary rgb monitor 75 second rgb monitor 3v or 5v figure 11. single supply rgb buffer figure 12 is an oscilloscope photo of the circuit in figure 11 operating from a 3 v supply and driven by the blue signal of a color bar pattern. note that the input and output are at ground during the horizontal blanking interval. the rgb signals are specified to output a maximum of 700 mv peak. the output of the ad8041 is 1.4 v with the termination resistors providing a divide-by-two. the red and green signals can be buffered in the same manner with duplication of this circuit. v in gnd gnd v out 10 0% 100 90 5 s 500mv 500mv figure 12. 3 v, rgb buffer single supply composite video line driver figure 13 shows a schematic of a single supply gain-of-two composite video line driver. since the sync tips of a composite video signal extend below ground, the input must be ac coupled and shifted positively to provide signal swing during these nega- tive excursions in a single supply configuration. the input is terminated in 75 ? and ac coupled via c in to a voltage divider that provides the dc bias point to the input. setting the optimal bias point requires some understanding of the nature of composite video signals and the video performance of the ad8041. signals of bounded peak-to-peak amplitude that vary in duty cycle require larger dynamic swing capability than their peak-to- peak amplitude after ac coupling. as a worst case, the dynamic signal swing required will approach twice the peak-to-peak value. the two bounding cases are for a duty cycle that is mostly low, but occasionally goes high at a fraction of a percent duty cycle and vice versa. composite video is not quite this demanding. one bounding extreme is for a signal that is mostly black for an entire frame, but has a white (full intensity), minimum width spike at least once per frame. the other extreme is for a video signal t hat is full white every- where. the blanking intervals and sync tips of such a signal will have neg ative going excursions in com pliance with composite video specifications. the combination of horizontal and vertical blanking intervals limit such a signal to being at its highest level (white) for only about 75% of the time. as a result of the duty cycle variations between the two extremes presented above, a 1 v p-p composite video signal that is multi- plied by a gain of two requires about 3.2 v p-p of dynamic voltage swing at the output for an op amp to pass a composite video signal of arbitrary duty cycle without distortion. some circuits use a sync tip clamp along with ac coupling to hold the sync tips at a relatively constant level in order to lower the amount of dynamic signal swing required. however, these circuits can have artifacts like sync tip compression unless they are driven by sources with very low output impedance. 6 4 7 3 2 ad8041 r f 1k 10k 10 f 5v 75 composite video in nc 0.1 f r t 75 8 1000 f 0.1 f 4.99k 10 f 4.99k 47 f r g 1k 220 f 75 coax r l 75 v out figure 13. single supply composite video line driver the ad8041 not only has ample signal swing capability to handle the dynamic range required without using a sync tip clamp, but also has good video specifications like differential gain and differential phase when buffering these signals in an ac coupled configuration.
rev. a C14C ad8041 to test this, the differential gain and differential phase were measured for the ad8041 while the supplies were varied. as the lower supply is raised to approach the video signal, the first effect to be observed is that the sync tips become compressed before the differential gain and differential phase are adversely affected. thus, there must be adequate swing in the negative direction to pass the sync tips without compression. as the upper supply is lowered to approach the video, the differ- ential gain and differential phase were not significantly adversely affected until the difference between the peak video output and the supply reached 0.6 v. thus, the highest video level should be kept at least 0.6 v below the positive supply rail. taking the above into account, it was found that the optimal point to bias the noninverting input is at 2.2 v dc. operating at this point, the worst case differential gain is measured at 0.06% and the worst case differential phase is 0.06 . the ac coupling capacitors used in the circuit at first glance appear quite large. a composite video signal has a lower fre- quency band edge of 30 hz. the resistances at the various ac coupling points especially at the output are quite small. in order to minimize phase shifts and baseline tilt, the large value capacitors are required. for video system performance that is not to be of the highest quality, the value of these capacitors can be reduced by a factor of up to five with only a slightly observ- able change in the picture quality. sync stripper some rgb monitor systems use only three cables total and carry the synchronizing signals along with the green (g) signal on the same cable. the sync signals are pulses that go in the negative direction from the blanking level of the g signal. in some applications like prior to digitizing component video signals with a/d converters, it is desirable to remove or strip the sync portion from the g signal. figure 14 is a schematic of a circuit using the ad8041 running on a single 5 v supply that performs this function. ad8041 r2 1k 10 f 0.1 f 0.8v (2x v blank ) 5v 75 v in 75 75 (monitor) r1 1k 7 6 3 2 4 green w/sync v blank +0.4 ground green w/out sync ground figure 14. single supply sync stripper refer ring to figure 15, the green plus sync signal is output from an adv7120, a single supply triple video dac. because the dac is single supply, the lowest level of the sync tip is at ground or slightly above. the ad8041 is set for a gain of two to compensate for the divide by two of the output terminations. 10 0% 100 90 10 s 500mv 500mv figure 15. single supply sync stripper the reference voltage for r1 should be twice the dc blanking level of the g signal. if the blanking level is at ground and the sync tip is negative as in some dual supply systems, then r1 can be tied to ground. in either case, the output will have the sync removed and have the blanking level at ground. layout considerations the specified high-speed performance of the ad8041 requires careful attention to board layout and component selection. proper rf design techniques and low-pass parasitic component selection are necessary. the pcb should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. the ground plane should be removed from the area near the input pins to reduce the stray capacitance. chip capacitors should be used for the supply bypassing (see figure 16). one end should be connected to the ground plane and the other within 1/8 inch of each power pin. an additional large (0.47 f 10 f) tantalum electrolytic capacitor should be connected in parallel, but not necessarily so close, to supply current for fast, large signal changes at the output. the feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. capacitance variations of less than 1 pf at the inverting input will significantly affect high-speed performance. stripline design techniques should be used for long signal traces (greater than about 1 inch). these should be desi gned with a characteristic impedance of 50 ? or 75 ? and be properly termi- nated at each end.
ad8041 rev. a C15C v+ in out v gnd vch 1 vcl so noninverter 1 analog devices figure 17. evaluation board silkscreen (top) evaluation board an evaluation board for the ad8041 is available which has been carefully laid out and tested to demonstrate that the specified high- speed performance of the device can be realized. for ordering information, please refer to the ordering guide. the layout of the evaluation board can be used as shown or can serve as a guide for a board layout. 6 8 7 3 2 ad8041 10 f 0.1 f 10k v in r o 75 4 1000 f 0.1 f 4.99k 10 f 4.99k 47 f r g 1k 220 f 10 f 0.1 f enable C v tp1 tp3 tp2 tp4 r f 1k j2 j1 j3 j4 j5 r t 75 +v figure 16. noninverting configurations for evaluation boards figure 18. board layout (component side) figure 19. board layout (back side) table i. recommended component values ad8041a gain component +1 +2 +2 +5 +10 r f 0 ? 2k ? 400 ? 2k ? 2k ? r g 2k ? 400 ? 500 ? 220 ? r o (nominal) 75 ? 75 ? 75 ? 75 ? 75 ? r t (nominal) 75 ? 75 ? 75 ? 75 ? 75 ? small signal bw (mhz) v s = 5 v 160 67 72 20 9 0.1 db bandwidth (mhz) v s = 5 v 7 32
rev. a C16C ad8041 8-lead plastic dip (n-8) 0.0110.003 (0.280.08) 0.30 (7.62) ref 15 0 0.10 (2.54) bsc seating plane 0.0350.01 (0.890.25) 0.180.03 (4.570.76) 0.033 (0.84) nom 0.0180.003 (0.460.08) 0.125 (3.18) min 0.1650.01 (4.190.25) 0.39 (9.91) max pin 1 4 5 8 1 0.25 (6.35) 0.31 (7.87) c01058C0C4/01(a) printed in u.s.a. 8-lead plastic soic (so-8) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 85 4 1 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) outline dimensions dimensions shown in inches and (mm). ad8041 revision history location page data sheet changed from rev. 0 to rev. a. specifications changed disable characteristics, off voltage (device disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8-lead ceramic dip (q-8) 1 4 85 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.055 (1.4) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38)

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